Stratix Memory Board I   --   README
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The directories outlined below contain files relevant to the Stratix 
Memory Board I (also referred to as SMB1).  For updated designs and 
documentation please visit MOLSON online at go.altera.com then click
Development Kits.


+readme.txt                             -this file
+bin                                    -(n/a)
   +common_files                        -(n/a)
+docs                                   -documentation
   +board_data_sheet                    -SMB1 datasheet
   +board_design_files                  -engineering docs and source
      +assembly_drawing                 -PCB Assembly dwg.
      +bill_of_materials                -PCB bill of materials
      +fabrication_drawing              -PCB Fab dwg.
      +max_config_controller            -MAX CPLD POF file
      +pcb_design_files                 -Allegro v14.2 board file
      +pcb_design_guidelines            -length matching, etc...
      +schematic                        -OrCAD v14.2 schematic & pdf
      +termination_spec                 -SMB1 termination spec
   +board_user_guide                    -SMB1 user guide
   +signal_integrity                    -SI simulations and results
      +device_models                    -relevent IBIS models
+examples                               -designs that use this board
   +hardware                            -hardware designs
      +demo_designs                     -demo designs
         +board_test_system             -bts GUI that excercises board
         +ddr1_devices                  -DDR1 devices test design sof
         +ddr1_dimm                     -DDR1 DIMM test design sof
         +rldram2_cio_devices           -RLDRAM2 CIO devices test design sof
         +rldram2_sio_devices           -RLDRAM2 SIO devices test design sof
      +lab_designs                      -(n/a)
      +reference_designs                -reference designs
         +golden_top                    -empty SMB1 top-level verilog 
                                         with pin assinment tcl script
   +production_test_files               -production test files
   +software                            -(n/a)


Minimum Requirements
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1)  Quartus 4.0 SP1
2)  USB-Blaster or ByteBlaster II.  (USB Blaster is prefered).


Known Issues
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1) ByteBlaster interface incorrectly uses 3.3V power (should be 1.8V)
   to power the buffers.  This makes JTAG very susceptable to SSN in
   Bank 4 which also has the DIMM interface.  If the DIMM design is
   running there can be issues even recognizing the JTAG chain. This
   can be avoided by hiting the Safe button (loads a design NOT
   Using DIMM) and then using the Altera programming cable. SignalTap
   with the DIMM design running can also incorrectly report 1's as 
   0's.  ByteBlaster II is slower and less susceptable to this issue
   than is the USB Blaster.
2) The RLDRAM2 memory interface cores are in beta stages so the design
   source for RLDRAM2 Devices have not been included in this CD release.
3) Production test assume MAX & Stratix are both in the JTAG chain 
   (SW4 setting).  The batch files also require the JTAG Server that
   is installed by Quartus 4.0SP1 or later because it uses new NIOS2
   features for flash burning.  Also needed are several DLLs and the
   Cygwin files that are installed by Quartus 4.0 SP1 and later. The
   BTS GUI batch files assume that only Stratix is in the chain.